`include "defines.v"
module if_id(
    input wire clk,
    input wire rst,
    input wire [31:0] inst_i,
    input wire [31:0] inst_addr_i,
    output wire [31:0] inst_addr_o,
    output wire [31:0] inst_o
);

// 将指令和指令地址打一拍
dff_set#(
    .DW       ( 32 )
)dff1(
    .clk      ( clk      ),
    .rst      ( rst      ),
    .set_data ( `INST_NOP ),
    .data_i   ( inst_i   ),
    .data_o   ( inst_o   )
);

dff_set#(
    .DW       ( 32 )
)u_dff_set(
    .clk      ( clk      ),
    .rst      ( rst      ),
    .set_data ( 32'd0 ),
    .data_i   ( inst_addr_i   ),
    .data_o   ( inst_addr_o   )
);



endmodule